LSI Design Engineering Service Offerings

Analog & Mixed-Signal

  • Excellent in analyzing and designing circuit
  • Proficient in layout, verification and debugging
  • Expert in using Cadence ADE, Specter, HSPICE, etc.
  • Experienced with a variety of process technology ranging from 0.6um, 0.5um, 0.35um, 130nm, 90nm, to 65nm process nodes
  • Experienced in testing of commercial Power Management ICs
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Analog Full-Custom Layout

  • Excellent in laying out Power Management IC (Buck, Boost, LDO, Charger, Power Banks and Wireless Charger)
  • Expert in using EDA tools such as Tanner Ledit, Tanner Hyper Verification, Cadence ADE , Cadence Dracula, Mentor Graphic Pyxis, Calibre LVS/DRC and PEX
  • Experienced in building Tcells/Pcells library on PDKs, Xreft, tech/display for new processes
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Digital/FPGA

  • Excellent in FPGA prototyping/ IP development (Encryption and authentication, PCIe to SATA converter, Hard Disk SSD, transferring data collected by sensors, ADCs… to ARM board, image processing for medical application)
  • Experienced in ARM based design, bus protocol (AHB, ABW, I2C, USB), NVM controller
  • Proficient in C/C++, Verilog, VHDL, System Verilog, System C, Matlab, scripting languages
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SoC Physical Implementation

  • Experienced in tapping out of Wireless, networking, ARM based MCU and digital platform Power Conversion SoCs chips
  • Expert in using Cadence/Synopsys physical design toolsets, Apache, Redhawk, Synopsys Design Compiler, Design Compiler Graphical (DCG), Primetime, Primetime PX, Synopys Galaxy Platform including ICC and StarRC, Cadence Conformal (LEC), Cadence conformal low power, RTL Compiler, RTL compiler physical (RCP), Apache PathFinder.
  • Experienced in low power design from architecture stages to physical implementation stages including: Refine power structure based on power requirement, knowledge of how to implement power reduction techniques (Dynamics power optimization, Multi-Vt optimization, clock gating, Voltage Islands, Dynamic Voltage Frequency Scaling (DVFS) and Adaptive Voltage Scaling (AVS) )
  • Experienced in process node of 28nm (20 mil gates 440MHz.)

Our customer success’ stories

Postage Meter and Mailroom Equipment

To keep the leading position in this highly competitive market, the client set a strategy to strengthen the research and development activities without increasing the cost, or do more with the same budget. An outsourcing service from a software company which can provide a large pool of highly skilled resources with a low labor cost is the right answer to this strategy.

See the solution

Audio System Development

The client developed the UniPhier Audio system, which had many components. It wanted to have an IT partner to develop 3 parts of the system, including:

  • Universal Asynchronous Receiver/Transmitter device driver to send and receive messages from test tool (PC side) using UART interface.
  • PNL to transfer and processing messages between UART device driver and PIF
  • PIF to implement media functionalities of UniPher Audio System

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